2 new people started:

• Richard Beneyton as cooperand (controls),
• Niko Neufeld as fellow (event-building)

Marianna Zuin has completed her diploma thesis and finished her time as technical student.
We thank Marianna for her great work and contributions.

Richard reported on the successful review of the TFC switch design.
Only small changes were proposed; the boards will be now 9U.
Prototypes expected Jan/Feb next year

For the Readout Supervisor most important functional blocks have been designed.
The FPGA programming and simulation has started
A first review of the design of the essential parts could be held in March, before Zbigniew leaves

Curro recapitulated the design of the RU prototype version II. The first prototype is expected for the 1^st week of December. Main changes are a streamlining of the design, less chips, fewer layers and consequently lower overall cost.

The modules for the RU could be ready and tested by end of Jan. 2001 The programming of the FPGA code for the FE->RU and RU->DAQ protocols is well under way and should also be ready by Jan. 2001 A behavioural model which represents the VHDL code is working, results on expected FIFO occupancy were shown.

Two people will leave the team by then - no short-term replacement is in sight.

Most important work for 2001 will consist of integration tests.

Niko reported about the contribution to DAQ 2000 at the NSS in Lyon. The event building on the Alteon NIC works. The time to handle a single event fragment is of the order of 10 us. This allows event building at an incoming rate of fragments of 100 kHz. After code re-organisation and optimisation the programs will be tested in the CMS test facility. (16 sources on 16 destinations) More understanding is needed of switches; in particular of flow control in a switching Gigabit Ethernet system.

Beat reported on the progress in building a test board for the CC PC. He presented a glue logic board, which will interface between the CC-PC and the connectors/protocols needed in LHCb. This allows to isolate the board design from the specific packaging/pin-out of the CC-PC. At the moment 4x I2c, 2x JTAG, 1x Parallel Port, 1x 10/100 BaseT RJ45 Ethernet, 1x RS 232 and a generic 32 bit parallel bus are provided The PC board should be ready by December.

The production of the MachZ based modules should go in production by next February, one or two sample modules should be available before this date.

Contributions to the forthcoming LHCb week were discussed. If an extensive presentation of the RU does not fit into the time-frame of the FE meeting it could be given in the Computing meeting, which is also plenary.